DocumentCode :
701417
Title :
Programmable bit-serial Reed-Solomon encoders
Author :
Fenn, S.T.J. ; Benaissa, M. ; Taylor, D. ; Luty, J.
Author_Institution :
School of Engineering, The University of Huddersfield, Queensgate, Huddersfield, HD1 3DH, U.K.
fYear :
1996
fDate :
10-13 Sept. 1996
Firstpage :
1
Lastpage :
4
Abstract :
In this paper the design of programmable bit-serial Reed-Solomon encoders is considered using the traditional Berlekamp multiplier. It is suggested that there are certain advantages to be gained by deriving the generator polynomial of the code using combinational logic, or equivalently using look-up tables, rather than using an iterative LFSR based approach. The use of the recently proposed Berlekamp-like bit-serial multiplier is also considered and shown to demonstrate a number of potential advantages over the traditional Berlekamp multiplier in Reed-Solomon encoders.
Keywords :
Clocks; Complexity theory; Galois fields; Generators; Logic gates; Polynomials; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Signal Processing Conference, 1996. EUSIPCO 1996. 8th
Conference_Location :
Trieste, Italy
Print_ISBN :
978-888-6179-83-6
Type :
conf
Filename :
7083143
Link To Document :
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