Circuit design perspectives for Ge FinFET at 10nm and beyond

Author

Sinha, S. ; Shifren, L. ; Chandra, V. ; Cline, B. ; Yeric, G. ; Aitken, R. ; Cheng, B. ; Brown, A.R. ; Riddet, C. ; Alexandar, C. ; Millar, C. ; Asenov, A.

Author_Institution

ARM Inc., Austin, TX, USA

fYear

2015

fDate

2-4 March 2015

Firstpage

57

Lastpage

60

Abstract

In this paper we study the circuit design implications of Ge vs. Si PMOS FinFETs at the 10 and 7nm nodes, using TCAD calibrated statistical compact models and the ARM predictive benchmarking flow. The ARM predictive flow incorporates advanced-node-relevant layouts, design rules, parasitic RC extraction and wire-loading. We present the first comprehensive simulation study evaluating Ge pFinFETs in a realistic circuit design context and show that the lack of a stressing mechanism, higher leakage and variability results in sub-optimal performance compared to Si in all circuit benchmark metrics.

Keywords

MOSFET; benchmark testing; germanium; network synthesis; semiconductor device models; semiconductor device testing; technology CAD (electronics); ARM predictive benchmarking flow; FinFET; Ge; PMOS; Si; TCAD; advanced-node-relevant layouts; circuit design; design rules; parasitic RC extraction; size 10 nm; size 7 nm; statistical compact models; wire-loading; Benchmark testing; Delays; FinFETs; Integrated circuit modeling; Logic gates; Performance evaluation; Silicon; Place; by; commas; here; keywords; separated;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ISQED), 2015 16th International Symposium on

Conference_Location

Santa Clara, CA

Print_ISBN

978-1-4799-7580-8

Type

conf

DOI

10.1109/ISQED.2015.7085398

Filename

7085398