Architectural reliability estimation using design diversity

Reliability has emerged as an important design criterion due to shrinking device dimensions. Several reliability estimation techniques have been proposed which apply either fault injection or analytical methods. Among all such techniques, design diversity, which is initially proposed to protect system from common-mode failures using redundant copies of different implementation, has been applied to quantify the availability of a duplex system in circuit-level design. In this paper, we utilize the design diversity metric for architecture-level reliability analysis and validate the concept with diverse processing architectures. A novel graph based analysis is introduced which jointly quantifies circuit-level design diversity and architecture-level operator exclusiveness. The proposed approach is demonstrated on several embedded computing architectures through the analysis on architecture and application-level design diversity, as well as estimation of system Mean-Time-to-Failure.