Analysis and optimization of flip-flops under process and runtime variations

Process and runtime variations affect the functionality of nanoscale VLSI designs which leads to reduced manufacturing yield and increased runtime failures. In this paper, a comparative analysis of the impact of process and runtime variations on the performance of flip-flops (FF) is carried out. Our analysis shows that independent consideration of the effect of different sources of variations may result in significant inaccuracy compared to the combined effect analysis, and leads to sub-optimal designs. In particular, our analysis reveals that the particular FF designs which are resilient to the process variation are not the best choices for the combined effects of process and runtime variations. Furthermore, we develop a framework to design and optimize resilient FFs against process and runtime variations. The results indicate that the framework is able to reduce the timing failure of FFs up to 99.5%.