Title :
The low power design of SM4 cipher with resistance to differential power analysis
Author :
Yanbo Niu ; Anping Jiang
Author_Institution :
Beijing Microelectron. Technol. Inst., Beijing, China
Abstract :
The 128-bit SM4[1] cipher is the first commercial cipher algorithm published by China in 2012, which is mainly used in WLAN. Comparing with conventional approaches, additive masking is adopted to resist the DPA (Differential Power Analysis) attack, and PPRM circuit structure is adopted to reduce the power consumption for SM4 S-box. Simulation results show that the design has a 50% reduction in power consumption and a 44% reduction in delay at the cost of area 20% increased using SMIC 0.18μm technology. Two sets of 2000 plaintext inputs are used in the DPA attack. Simulation results show the resistance of S-box to DPA is reliable. Additionally, 4-stage-pipelined SM4 cipher circuit is realized with an area of 18609 gates. The throughput rate of it can reach 2Gbps with a power consumption of 3.65mW@10Mhz.
Keywords :
cryptography; delays; low-power electronics; power consumption; 4-stage-pipelined SM4 cipher circuit; China; DPA attack; PPRM circuit structure; SM4 S-box resistance; SMIC technology; WLAN; additive masking; area cost; delay reduction; differential power analysis; frequency 10 MHz; low power design; plaintext inputs; power 3.65 mW; power consumption reduction; size 0.18 mum; word length 128 bit; Additives; Ciphers; Encryption; Logic gates; Power demand; Resistance; Throughput; PPRM; S-box; SM4-cipher; additive masking;
Conference_Titel :
Quality Electronic Design (ISQED), 2015 16th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-7580-8
DOI :
10.1109/ISQED.2015.7085471
