DocumentCode
702353
Title
Optimization of the FPGA parallel image processor
Author
Brylski, Przemyslaw ; Strzelecki, Michal
Author_Institution
Inst. of Electron., Tech. Univ. of Lodz, Lodz, Poland
fYear
2012
fDate
27-29 Sept. 2012
Firstpage
183
Lastpage
188
Abstract
This paper describes a hardware implementation of parallel digital image processor in FPGA technology. The architecture and algorithm modifications presented in this paper are aimed to enable fully parallel processing and reduction of FPGA resources. The circuit core is 64×64 array for image processing and analysis. The proposed processor was tested on labeling of binary images; obtained analysis results are presented and discussed.
Keywords
circuit optimisation; field programmable gate arrays; image processing; parallel processing; FPGA parallel image processor optimization; FPGA resources; FPGA technology; algorithm modifications; binary images; circuit core; hardware implementation; image analysis; image processing; parallel processing; parallel reduction; Abstracts; Decision support systems; Digital images; Electronic mail; Field programmable gate arrays; Hardware; Optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
New Trends in Audio & Video and Signal Processing: Algorithms, Architectures, Arrangements, and Applications (NTAV/SPA), 2012 Joint Conference
Conference_Location
Lodz
Print_ISBN
978-8-3728-3502-4
Type
conf
Filename
7085533
Link To Document