• DocumentCode
    702649
  • Title

    An FPGA Correlation-Edge Distance approach for disparity map

  • Author

    Aguilar-Gonzalez, Abiel ; Perez-Patricio, Madain ; Arias-Estrada, Miguel ; Camas-Anzueto, Jorge-Luis ; Hernandez-de Leon, Hector-Ricardo ; Sanchez-Alegria, Avisai

  • Author_Institution
    Inst. Tecnol. de Tuxtla Gutierrez, Túxtla Gutiérrez, Mexico
  • fYear
    2015
  • fDate
    25-27 Feb. 2015
  • Firstpage
    21
  • Lastpage
    28
  • Abstract
    This paper describes an FPGA Correlation-Edge Distance approach for real time disparity map generation in stereo-vision. The proposed method calculates the disparity map for the input and disparity map for Edge Distance images of a stereopair. In both cases the approximation algorithm of disparity map SAD (Sum of Absolute Differences) is used. The final disparity map is determined from the previously generated maps, considering a homogeneity parameter defined for each point in the scene. Due to low complexity when implementing stereo-vision algorithms in FPGA devices, the proposed method was implemented in a Cyclone II EP2C35F672C6 FPGA assembled in an Altera DE2 breadboard. The developed module can process stereo-pairs of 1280×1024 pixel resolution at a rate of 75 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 63 pixels. The presented architecture provides a significant improvement in regions with uniformed texture over correlation based stereo-vision algorithms in the reported literature and an accelerated processing rate.
  • Keywords
    edge detection; field programmable gate arrays; image resolution; stereo image processing; Altera DE2 breadboard; Cyclone II EP2C35F672C6 FPGA; FPGA correlation edge distance approach; FPGA devices; SAD; approximation algorithm; edge distance images; final disparity map; pixel resolution; real time disparity map generation; stereo vision algorithms; stereopair; sum of absolute differences; Computer architecture; Correlation; Field programmable gate arrays; Image edge detection; Image resolution; Real-time systems; Signal processing algorithms; Disparity map; FPGA; Verilog;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Communications and Computers (CONIELECOMP), 2015 International Conference on
  • Conference_Location
    Cholula
  • Type

    conf

  • DOI
    10.1109/CONIELECOMP.2015.7086952
  • Filename
    7086952