• DocumentCode
    702662
  • Title

    Different Approaches For Implementation of Viterbi decoder on reconfigurable platform

  • Author

    Mandwale, Amruta J. ; Mulani, Altaf O.

  • Author_Institution
    Electron. & Telecommun. Dept., SKN Sinhgad Coll. of Eng., Pandharpur, India
  • fYear
    2015
  • fDate
    8-10 Jan. 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Generally, the data transmitted over any communication channel is affected due to noise. So, for detecting and correcting the errors due to channel noise, encoding and decoding should be performed at the transmitter and receiver end respectively. The Viterbi algorithm is used in many communication channels for decoding convolutional codes. Using VLSI technology, the system requires low power, less area and high speed constraints while designing. Because of different steps for designing Viterbi Decoder speed of designing is limited. In this paper, different kind of implementation of Viterbi decoder along with their performance has been discussed.
  • Keywords
    VLSI; Viterbi decoding; convolutional codes; telecommunication channels; VLSI technology; Viterbi algorithm; Viterbi decoder; communication channels; convolutional codes; reconfigurable platform; Computer architecture; Decoding; Measurement; Random access memory; Receivers; Transistors; Viterbi algorithm; Adaptive viterbi decoder; FPGA; GDIL; Non-polynomial-approach; Register exchange; VLSI; Viterbi decoder;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Pervasive Computing (ICPC), 2015 International Conference on
  • Conference_Location
    Pune
  • Type

    conf

  • DOI
    10.1109/PERVASIVE.2015.7086976
  • Filename
    7086976