Design of CMOS ternary logic family based on single supply voltage

Since inception, CMOS logic is considered for implementation of only binary logic. As the circuit complexity is increasing, the interconnection in binary occupies large area on a VLSI chip and thus, degrading the performance of binary. Hence the non binary higher radix logic which is called as multi valued logic (MVL) is considered as solution to this issue. A ternary logic or a three-valued logic is considered as the best radix of several MVL systems. In this paper, the designs of ternary logic circuits are proposed based on single power supply voltage. The proposed ternary logic gates are useful in designing the ternary logic circuits. The proposed designs are based on the use of only enhancement type MOSFETS so that it can be implemented with recent CMOS technology. The design of a set of inverters and basic ternary logic gates is proposed. The transistor count in the basic ternary gates is being reduced thereby improving component density. The proposed GATES are designed & simulated with the help of Microwind EDA tool & can be implemented at its layout side using VLSI CMOS technology.