Automated parallel-pipeline structure of FFT hardware design for real-time multidimensional signal processing

Offered algorithm allows to build the structure of the parallel pipeline FFT processors (PPFFT-processor) computing the vector DFT in real time with the minimum structural complexity at given parameters: speed of input data receipt; structure of a computing element (arithmetic device) and time of the butterfly operation execution. The considered approach to structural synthesis of the PPFFT-processors for R-dimensional signal processing allows to receive the structure of the processor under given restrictions of a specific problem and is the basis for resolving the questions of automated design of PPFFT-processors at a structural level.