• DocumentCode
    703534
  • Title

    Efficient bit-level design of an on-board digital TV demultiplexer

  • Author

    Calvo, S. ; Sala, J. ; Pages, A. ; Vazquez, G.

  • Author_Institution
    Dept. of Signal Theor. & Commun., Univ. Politec. de Catalunya, Barcelona, Spain
  • fYear
    1998
  • fDate
    8-11 Sept. 1998
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A bit-level description of the signal processing stage of an on-board integrated VLSI multi-carrier demodulator is presented in this paper, along with a description of the optimization procedure that has been developed for the signal processing functions1. The demultiplexer is capable of handling a varying number of carriers in a 36 MHz bandwidth on the satellite up-link. Its architecture has been optimized at bit-level in a way dependent on the known input signal statistics and carrier distributions allowed by the frequency plan.
  • Keywords
    VLSI; demultiplexing equipment; digital television; signal processing; bit-level design; carrier distributions; input signal statistics; on-board digital TV demultiplexer; on-board integrated VLSI multicarrier demodulator; optimization procedure; satellite up-link; signal processing functions; Complexity theory; Demodulation; Demultiplexing; Histograms; Logic gates; Optimization; Program processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Conference (EUSIPCO 1998), 9th European
  • Conference_Location
    Rhodes
  • Print_ISBN
    978-960-7620-06-4
  • Type

    conf

  • Filename
    7090005
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=703534