Title :
Reduced current harmonics in the NPC inverter with a novel space vector PWM
Author :
Pratheesh, K.J. ; Jagadanand, G. ; Ramchand, Rijil
Author_Institution :
Electr. Eng. Dept., Nat. Inst. of Technol., Calicut, India
Abstract :
The three-phase three-level diode clamped inverter, due to its supreme performance compared to a two-level inverter is one of the widely used multilevel inverter topology for medium voltage, high power applications. One of the popular control strategies for these inverters is space vector pulse width modulation (SVPWM) which has superior advantages in terms of its implementation and harmonic reduction. A three-level neutral point clamped (NPC) inverter with space vector modulation is presented in this paper. Duty cycles of the inverter switches are calculated based on a two-level inverter space vector diagram. A switching sequence is proposed in this paper to reduce the Total Harmonic Distortion (THD) in the line current as well as to increase the DC bus utilization of the inverter. The current harmonics of conventional SVPWM based inverter is compared for various modulation indices with the new modulation method and the result is encouraging.
Keywords :
PWM invertors; power conversion harmonics; power semiconductor diodes; power semiconductor switches; NPC inverter; SVPWM based inverter; current harmonic reduction; duty cycle calculation; inverter switches; modulation indices; multilevel inverter topology; space vector PWM; space vector pulse width modulation; three-level neutral point clamped inverter; three-phase three-level diode clamped inverter; total harmonic distortion reduction; Decision support systems; Current Harmonic Distortion; Diode Clamped Topology; Neutral Point Clamping; Space Vector Pulse Width Modulation; Three phase Multilevel inverter; switching sequence;
Conference_Titel :
Signal Processing, Informatics, Communication and Energy Systems (SPICES), 2015 IEEE International Conference on
Conference_Location :
Kozhikode
DOI :
10.1109/SPICES.2015.7091399