DocumentCode
703850
Title
A unified hardware/software MPSoC system construction and run-time framework
Author
Skalicky, Sam ; Schmidt, Andrew G. ; Lopez, Sonia ; French, Matthew
Author_Institution
Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
fYear
2015
fDate
9-13 March 2015
Firstpage
301
Lastpage
304
Abstract
With the continual enhancement of heterogeneous resources in FPGA devices, utilizing these resources becomes a challenging burden for developers. Especially with the inclusion of sophisticated multiple processor system-on-chips, the necessary skill set to effectively leverage these resources spans both hardware and software expertise. The maturation of high level synthesis tools and programming languages aim to alleviate these complexities, yet there still exist systematic gaps that must be bridged to provide a more cohesive hardware/software development environment. High level MPSoC design initiatives such as Redsharc have reduced the costs of entry, simplifying application implementation. We propose a unified hardware/software framework for system construction, leveraging Redsharc´s APIs, efficient on-chip interconnects, and run-time controllers. We present system level abstractions that enable compilation and implementation tools for hardware and software to be merged into a single configurable system development environment. Finally, we demonstrate our proposed framework with Redsharc, using AES encryption/decryption spanning software implementations on ARM and MicroBlaze processors and hardware kernels.
Keywords
field programmable gate arrays; high level synthesis; integrated circuit interconnections; microprocessor chips; programming languages; system-on-chip; ARM processors; FPGA devices; MPSoC system construction; MicroBlaze processors; Redsharc; hardware kernels; heterogeneous resources; high level synthesis tools; multiple processor system-on-chips; on-chip interconnects; programming languages; run-time controllers; run-time framework; system level abstractions; systematic gaps; Encryption; Field programmable gate arrays; Hardware; Kernel; Process control; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location
Grenoble
Print_ISBN
978-3-9815-3704-8
Type
conf
Filename
7092402
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