Title :
A score-based classification method for identifying Hardware-Trojans at gate-level netlists
Author :
Oya, Masaru ; Youhua Shi ; Yanagisawa, Masao ; Togawa, Nozomu
Author_Institution :
Dept. of Comput. Sci. & Commun. Eng., Waseda Univ., Tokyo, Japan
Abstract :
Recently, digital ICs are often designed by outside vendors to reduce design costs in semiconductor industry, which may introduce severe risks that malicious attackers implement Hardware Trojans (HTs) on them. Since IC design phase generates only a single design result, an RT-level or gate-level netlist for example, we cannot assume an HT-free netlist or a Golden netlist and then it is too difficult to identify whether a generated netlist is HT-free or HT-inserted. In this paper, we propose a score-based classification method for identifying HT-free or HT-inserted gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be “HT-inserted” and all the HT-free gate-level benchmarks to be “HT-free” in approximately three hours for each benchmark.
Keywords :
benchmark testing; feature extraction; integrated circuit design; invasive software; pattern classification; semiconductor industry; Golden netlist; HT-free gate-level benchmarks; HT-free netlist; HT-inserted gate-level benchmarks; HT-inserted netlist; IC design phase; RT-level netlist; Trojan net feature extraction; Trust-HUB gate-level benchmarks; digital ICs; gate-level netlist; hardware-trojan identification; malicious attackers; score-based classification method; semiconductor industry; Adders; Benchmark testing; Feature extraction; Integrated circuits; Logic gates; Logic testing; Trojan horses; classification; gate-level netlist; golden-IC free; hardware Trojans; identification;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8