Title :
Worst-case communication time analysis of networks-on-chip with shared virtual channels
Author :
Rambo, Eberle A. ; Ernst, Rolf
Author_Institution :
Inst. of Comput. & Network Eng., Tech. Univ. Braunschweig, Braunschweig, Germany
Abstract :
Network-on-Chip (NoC) based multi- and many-core architectures show high potential for use in real-time applications due to their superior efficiency. In real-time systems, it is necessary to guarantee that the application´s timing requirements are met through the analysis of the worst-case behavior. A typical approach to guarantee real-time is the exclusive assignment of virtual channels to tasks or cores. Virtual channels, however, are a limited resource in NoCs. In future systems, there will be more tasks than virtual channels (VCs) in the network. In this paper, we propose a worst-case communication analysis of wormhole-switched best-effort NoCs (no special QoS mechanism) with SLIP arbitration and support to shared VCs. The approach is based on Compositional Performance Analysis, which enables non-symmetrical guarantees for the streams. The analysis is evaluated experimentally and compared with simulation and related work.
Keywords :
multiprocessing systems; multiprocessor interconnection networks; network-on-chip; real-time systems; timing; NoC based many-core architectures; SLIP arbitration; compositional performance analysis; network-on-chip based multi-core architectures; nonsymmetrical guarantees; real-time systems; timing requirements; virtual channels; wormhole-switched best-effort NoC; worst-case communication analysis; Analytical models; Interference; Ports (Computers); Real-time systems; Round robin; Switches; Time factors;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8