DocumentCode :
703968
Title :
Feedback-bus oscillation ring: A general architecture for delay characterization and test of interconnects
Author :
Shi-Yu Huang ; Meng-Ting Tsai ; Kun-Han Hans Tsai ; Wu-Tung Cheng
Author_Institution :
Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
924
Lastpage :
927
Abstract :
In this paper we propose a flexible delay characterization and test architecture, called Feedback-Bus Oscillation Ring (FB-OR), for die-to-die interconnects in a 3D IC. As compared to previous works, it is unique in its ability to streamline the characterization/test operations for a set of arbitrary interconnects with multiple pins sprawling multiple dies. During the Design-for-Testability stage, one common feedback-bus (connected to all dies in the IC under characterization/test) is inserted. Through this feedback-bus, an oscillation ring can be formed dynamically and the Variable-Output-Threshold (VOT) technique can be applied to characterize the delay of one interconnect segment at a time. Experimental results indicate that this method is not only flexible and scalable, but requiring only a small area overhead.
Keywords :
design for testability; feedback oscillators; integrated circuit interconnections; three-dimensional integrated circuits; 3D IC; FB-OR; VOT technique; arbitrary interconnects; design-for-testability stage; die-to-die interconnects; feedback-bus oscillation ring; flexible delay characterization; test architecture; variable-output-threshold technique; Circuit faults; Delays; Integrated circuit interconnections; Inverters; Oscillators; Testing; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092520
Link To Document :
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