DocumentCode :
703985
Title :
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm
Author :
Hanyu, Takahiro ; Suzuki, Daisuke ; Onizawa, Naoya ; Matsunaga, Shoun ; Natsui, Masanori ; Mochizuki, Akira
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
1006
Lastpage :
1011
Abstract :
Novel logic-LSI architecture, called “spintronics-based nonvolatile logic-in-memory (NV-LIM) architecture,” where nonvolatile spintronic storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic-LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.
Keywords :
CMOS integrated circuits; VLSI; integrated circuit reliability; logic circuits; logic design; low-power electronics; magnetoelectronics; random-access storage; CMOS; VLSI computing paradigm; logic-LSI architecture; logic-circuit plane; nonvolatile spintronic storage elements; spintronics-based nonvolatile logic-in-memory architecture; Computer architecture; Delays; Logic gates; Magnetic tunneling; Nonvolatile memory; Random access memory; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092537
Link To Document :
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