DocumentCode
703998
Title
Transparent linking of compiled software and synthesized hardware
Author
Thomas, David B. ; Fleming, Shane T. ; Constantinides, George A. ; Ghica, Dan R.
Author_Institution
Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
fYear
2015
fDate
9-13 March 2015
Firstpage
1084
Lastpage
1089
Abstract
Modern heterogeneous devices contain tightly coupled CPU and FPGA logic, allowing low latency access to accelerators. However, designers of the system need to treat accelerated functions specially, with device specific code for instantiating, configuring, and executing accelerators. We present a system level linker, which allows functions in hardware and software to be linked together to create heterogeneous systems. The linker works with post-compilation and post-synthesis components, allowing the designer to transparently move functions between devices simply by linking in either hardware or software object files. The linker places no special emphasis on the software, allowing computation to be initiated from within hardware, with function calls to software to provide services such as file access. A strong type-system ensures that individual code artifacts can be written using the conventions of that domain (C, HLS, VHDL), while allowing direct and transparent linking.
Keywords
field programmable gate arrays; high level synthesis; FPGA logic; accelerators; compiled software; coupled CPU; device specific code; file access; heterogeneous systems; low latency access; modern heterogeneous devices; post-compilation; post-synthesis components; software object files; strong type-system; synthesized hardware; system level linker; transparent linking; Field programmable gate arrays; Hardware; IP networks; Joining processes; Protocols; Servers; Software;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location
Grenoble
Print_ISBN
978-3-9815-3704-8
Type
conf
Filename
7092550
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