DocumentCode
703999
Title
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation
Author
Psarras, A. ; Seitanidis, I. ; Nicopoulos, C. ; Dimitrakopoulos, G.
Author_Institution
Electr. & Comput. Eng, Democritus Univ. of Thrace, Xanthi, Greece
fYear
2015
fDate
9-13 March 2015
Firstpage
1090
Lastpage
1095
Abstract
The efficiency of modern Networks-on-Chip (NoC) is no longer judged solely by their physical scalability, but also by their ability to deliver high performance, Quality-of-Service (QoS), and flow isolation at the minimum possible cost. Although traditional architectures supporting Virtual Channels (VC) offer the resources for flow partitioning and isolation, an adversarial workload can still interfere and degrade the performance of other workloads that are active in a different set of VCs. In this paper, we present PhaseNoC, a truly non-interfering VC-based architecture that adopts Time-Division Multiplexing (TDM) at the VC level. Distinct flows, or application domains, mapped to disjoint sets of VCs are isolated, both inside the router´s pipeline and at the network level. Any latency overhead is minimized by appropriate scheduling of flows in separate phases of operation, irrespective of the chosen topology. The resulting design yields significant reductions in the area/delay cost of the network. Experimental results corroborate that - with lower cost than state-of-the-art NoC architectures, and with minimum latency overhead - we remove any flow interference and allow for efficient network traffic isolation.
Keywords
telecommunication channels; telecommunication network routing; telecommunication scheduling; telecommunication traffic; time division multiplexing; NoC architectures; PhaseNoC; QoS; TDM scheduling; VC-based architecture; flow interference; flow isolation; flow partitioning; network traffic isolation; networks-on-chip; quality-of-service; router pipeline; time-division multiplexing; virtual-channel level; Pipeline processing; Pipelines; Resource management; Schedules; Switches; Throughput; Time division multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location
Grenoble
Print_ISBN
978-3-9815-3704-8
Type
conf
Filename
7092551
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