DocumentCode
704012
Title
Quick error detection tests with fast runtimes for effective post-silicon validation and debug
Author
Lin, David ; Eswaran, S. ; Kumar, Sharad ; Rentschler, Eric ; Mitra, Subhasish
Author_Institution
Dept. of EE, Stanford Univ., Stanford, CA, USA
fYear
2015
fDate
9-13 March 2015
Firstpage
1168
Lastpage
1173
Abstract
Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED).
Keywords
elemental semiconductors; error detection; integrated circuit testing; logic testing; silicon; system-on-chip; OpenSPARC T2-like multi-core SoC; Si; debug; error detection latencies; post-silicon validation tests; quick error detection tests; software-only QED; Arrays; Cache memory; Clocks; Computer bugs; Memory architecture; Runtime; System-on-chip; Debug; Post-Silicon Validation; Quick Error Detection;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location
Grenoble
Print_ISBN
978-3-9815-3704-8
Type
conf
Filename
7092564
Link To Document