DocumentCode :
704033
Title :
A tool for the assisted design of charge redistribution SAR ADCs
Author :
Brenna, S. ; Bonetti, A. ; Bonfanti, A. ; Lacaita, A.L.
Author_Institution :
DEIB, Politec. di Milano, Milan, Italy
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
1265
Lastpage :
1268
Abstract :
The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic effects in the feedback charge-redistribution DAC. Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical tool (CSAtool) to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances thus computing both differential and integral nonlinearity (DNL, INL). SNDR and ENoB degradation due to static non-linear effects is also estimated. An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 104 shorter simulation time, allowing a large number statistical simulations which would be otherwise impracticable. Measurements on two fabricated SAR ADCs confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and predict its static and dynamic metrics.
Keywords :
analogue-digital conversion; circuit simulation; digital-analogue conversion; mathematics computing; statistical analysis; CSAtool; ENoB degradation; MATLAB-based numerical tool; SNDR; analog-to-digital converters; array topology; capacitive mismatch; charge redistribution SAR ADC assisted design; circuit design environments; circuit simulator; complex calculations; custom modeling; differential nonlinearity; digital-to-analog converter; dynamic metrics; feedback charge-redistribution DAC; heavy simulations; integral nonlinearity; parametric simulation; parasitic capacitances; parasitic effects; static metrics; static nonlinear effect; statistical simulation; stray capacitances; successive approximation register; Arrays; Capacitance; Capacitors; Computational modeling; Integrated circuit modeling; Numerical models; Topology; Analog-to-digital conversion; assisted design; charge redistribution successive approximation registers ADC; numerical tools;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092585
Link To Document :
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