Title :
Detection of asymmetric aging-critical voltage conditions in analog power-down mode
Author :
Zwerger, Michael ; Graeb, Helmut
Author_Institution :
Inst. for Electron. Design Autom., Tech. Univ. Munchen, Munich, Germany
Abstract :
In this work, a new verification method for the power-down mode of analog circuit blocks is presented. In power-down mode, matched transistors can be stressed with asymmetric voltages. This will cause time-dependent mismatch due to transistor aging. In order to avoid reliability problems, a new method for automatic detection of asymmetric power-down stress conditions is presented. Therefore, power-down voltage-matching rules are formulated. The method combines structural analysis and voltage propagation. Experimental results demonstrate the efficiency and effectiveness of the approach.
Keywords :
ageing; analogue integrated circuits; integrated circuit reliability; transistors; analog circuit blocks; analog power-down mode; asymmetric aging-critical voltage conditions detection; asymmetric power-down stress condition detection; matched transistors; power-down voltage-matching rules; reliability problem avoidance; structural analysis; time-dependent mismatch; transistor aging; voltage propagation; Aging; Analog circuits; Libraries; Logic gates; Pins; Reliability; Transistors;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8