DocumentCode :
704066
Title :
A new approximate adder with low relative error and correct sign calculation
Author :
Junjun Hu ; Weikang Qian
Author_Institution :
Joint Inst., Shanghai Jiao Tong Univ., Shanghai, China
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
1449
Lastpage :
1454
Abstract :
Conventional precise adders need long delay and large power consumption to obtain accurate results. However, in recognition of the error tolerance of some applications such as multimedia processing and machine learning, a few recent works proposed approximate adders that generate inaccurate results occasionally to reduce the delay and power consumption. However, existing approximate adders rarely control the relative error and the potential sign error of the calculation results. In this paper, we propose a novel approximate adder that exploits the generate signals for carry speculation. Furthermore, we introduce a very low-cost error reduction module to effectively control the maximal relative error and a low-overhead sign correction module to fix the sign errors. Compared to the conventional adders, our adder is up to 4.3x faster and saves 47% power for a 32bit addition. Compared to the existing approximate adders, our adder significantly reduces the maximal relative error and ensures correct sign calculation with comparable area, delay, and power consumption.
Keywords :
adders; error analysis; approximate adder; carry speculation; correct sign calculation; delay reduction; error reduction module; error tolerance recognition; low-overhead sign correction module; machine learning; multimedia processing; potential sign error; power consumption; relative error; Adders; Bismuth; Delays; Error analysis; Generators; Power demand; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092618
Link To Document :
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