DocumentCode :
704134
Title :
Optimized Core-Links for Low-Latency NoCs
Author :
Kawano, Ryuta ; Tade, Seiichi ; Fujiwara, Ikki ; Matsutani, Hiroki ; Amano, Hideharu ; Koibuchi, Michihiro
Author_Institution :
Keio Univ., Yokohama, Japan
fYear :
2015
fDate :
4-6 March 2015
Firstpage :
172
Lastpage :
176
Abstract :
In recent many-core architectures, the number of cores has been steadily increasing and thus the network latency between cores becomes an important issue for parallel application programs. Because packet-switched network structures are widely used for core-to-core communications, a topology among cores has a major impact on the network latency. It has been reported that a small-world Network-on-Chip that adds links between randomly-selected routers on a regular router topology is effective for reducing the network latency. In this study, we extend this framework by connecting multiple links between a single core and quasi-optimally selected neigh boring routers to form multiple links from each core on a 2D MESH router topology. Results obtained by a flit-level discrete event simulator show that our optimized core-link topologies can achieve the average latency up to 48% lower than that of baseline topologies. Furthermore, full-system CMP simulation results show that by using optimized core-links we can improve the application execution time on the NAS Parallel Benchmarks by up to 10.1%.
Keywords :
benchmark testing; discrete event simulation; multiprocessing systems; network routing; network topology; network-on-chip; packet switching; parallel architectures; 2D MESH router topology; NAS parallel benchmarks; core-to-core communications; flit-level discrete event simulator; full-system CMP simulation; low-latency NoC; many-core architectures; network latency; optimized core-link topologies; optimized core-links; packet-switched network structures; parallel application programs; quasioptimally selected neighboring routers; randomly-selected routers; regular router topology; small-world network-on-chip; Network topology; Ports (Computers); Routing; Standards; System-on-chip; Topology; Wires; Network-on-Chip (NoC); Small-world network; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel, Distributed and Network-Based Processing (PDP), 2015 23rd Euromicro International Conference on
Conference_Location :
Turku
ISSN :
1066-6192
Type :
conf
DOI :
10.1109/PDP.2015.15
Filename :
7092716
Link To Document :
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