• DocumentCode
    704736
  • Title

    Graph-matching-based simulation-region selection for multiple binaries

  • Author

    Yount, Charles ; Patil, Harish ; Islam, Mohammad S. ; Srikanth, Aditya

  • fYear
    2015
  • fDate
    29-31 March 2015
  • Firstpage
    52
  • Lastpage
    61
  • Abstract
    Comparison of simulation-based performance estimates of program binaries built with different compiler settings or targeted at variants of an instruction set architecture is essential for software/hardware co-design and similar engineering activities. Commonly-used sampling techniques for selecting simulation regions do not ensure that samples from the various binaries being compared represent the same source-level work, leading to biased speedup estimates and difficulty in comparative performance debugging. The task of creating equal-work samples is made difficult by differences between the structure and execution paths across multiple binaries such as variations in libraries, in-lining, and loop-iteration counts. Such complexities are addressed in this work by first applying an existing graph-matching technique to call and loop graphs for multiple binaries for the same source program. Then, a new sequence-alignment algorithm is applied to execution traces from the various binaries, using the graph-matching results to define intervals of equal work. A basic-block profile generated for these matched intervals can then be used for phase-detection and simulation-region selection across all binaries simultaneously. The resulting selected simulation regions match both in number and the work done across multiple binaries. The application of this technique is demonstrated on binaries compiled for different Intel 64 Architecture instruction-set extensions. Quality metrics for speedup estimation and an example of applying the data for performance debugging are presented.
  • Keywords
    graph theory; hardware-software codesign; instruction sets; multiprocessing systems; program compilers; program debugging; Intel 64 architecture instruction-set extensions; block profile; call graphs; compiler settings; execution traces; graph-matching technique; graph-matching-based simulation-region selection; instruction set architecture; loop graphs; performance debugging; phase-detection; program binaries; quality metrics; sequence-alignment algorithm; simulation-based performance estimates; software/hardware co-design; source program; speedup estimation; Benchmark testing; Data models; Debugging; Heuristic algorithms; Program processors; Symmetric matrices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Performance Analysis of Systems and Software (ISPASS), 2015 IEEE International Symposium on
  • Conference_Location
    Philadelphia, PA
  • Type

    conf

  • DOI
    10.1109/ISPASS.2015.7095784
  • Filename
    7095784