Title :
Analyzing graphics processor unit (GPU) instruction set architectures
Author :
Mayank, Kothiya ; Hongwen Dai ; Jizeng Wei ; Huiyang Zhou
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
Because of their high throughput and power efficiency, massively parallel architectures like graphics processing units (GPUs) become a popular platform for generous purpose computing. However, there are few studies and analyses on GPU instruction set architectures (ISAs) although it is wellknown that the ISA is a fundamental design issue of all modern processors including GPUs.
Keywords :
computer architecture; graphics processing units; instruction sets; GPU instruction set architectures; ISA; generous purpose computing; graphics processor unit analysis; massively parallel architectures; processor design; Assembly; Benchmark testing; Computer architecture; Graphics processing units; Hardware; Process control; Registers;
Conference_Titel :
Performance Analysis of Systems and Software (ISPASS), 2015 IEEE International Symposium on
Conference_Location :
Philadelphia, PA
DOI :
10.1109/ISPASS.2015.7095794
