DocumentCode :
704756
Title :
Reciprocal abstraction for computer architecture co-simulation
Author :
Moeng, Michael ; Jones, Alex ; Melhem, Rami
Author_Institution :
Comput. Sci. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA
fYear :
2015
fDate :
29-31 March 2015
Firstpage :
268
Lastpage :
277
Abstract :
Co-simulation of computer architecture elements at different levels of abstraction and fidelity is becoming an increasing necessity for efficient experimentation and research. We propose reciprocal abstraction for computer architecture cosimulation, which allows the integration of simulation methods that utilize different levels of abstraction and fidelity of simulation. Further, reciprocal abstraction avoids the need to conduct detailed evaluations of individual computer architecture components entirely in a vacuum, which can lead to significant inaccuracies from ignoring the system context. Moreover, it allows an exploration of the impact on the full system resulting from design choices in the detailed component model. We demonstrate the potential inaccuracies of isolated component simulation. Using reciprocal abstraction, we integrate a parallel cycle-level networkon- chip (NoC) component into a detailed but more coarse-grain full system simulator.We show that co-simulation using reciprocal abstraction of the cycle-level network model reduces packet latency error compared to the more abstract network model by 69% on average. Additionally, as simulating a detailed network at the cycle-level can greatly increase simulation time over an abstract model, we implemented detailed network simulator using a GPU coprocessor. The CPU+GPU can reduce simulation time for the reciprocal abstraction co-simulation by 16% for a 256-core target machine and 65% for a 512-core target machine.
Keywords :
computer architecture; coprocessors; graphics processing units; network-on-chip; GPU coprocessor; NoC component; abstraction level; coarse-grain full system simulator; computer architecture cosimulation; fidelity level; graphics processing unit; network simulator; packet latency error; parallel cycle-level network-on-chip component; reciprocal abstraction; Computational modeling; Load modeling; Multicore processing; Pipelines; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Performance Analysis of Systems and Software (ISPASS), 2015 IEEE International Symposium on
Conference_Location :
Philadelphia, PA
Type :
conf
DOI :
10.1109/ISPASS.2015.7095812
Filename :
7095812
Link To Document :
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