• DocumentCode
    706149
  • Title

    Automatic code generation for multi-microblaze system with syndex

  • Author

    Pengcheng Mu ; Raulet, Mickael ; Nezan, Jean-Francois ; Cousin, Jean-Gabriel

  • Author_Institution
    IETR/Image & Remote Sensing Group, INSA Rennes, Rennes, France
  • fYear
    2007
  • fDate
    3-7 Sept. 2007
  • Firstpage
    1644
  • Lastpage
    1648
  • Abstract
    Image processing applications such as video codecs represent a great challenge in terms of real-time embedded systems. Programmable multicomponent architectures can provide suitable target solutions combining flexibility and computation power. Integrating multicomponents on FPGA provides greater flexibility but presents more challenges in system level design e.g. design space exploration, multiprocessor distribution and scheduling, inter-processor communications and real-time constraints. The aim of our work is to develop a fast automatic design process dedicated to the implementation of deterministic image processing applications on parallel multicomponent architectures. This design process is based on AAA methodology using the SynDEx CAD tool. A distributed implementation from high-level application and architecture descriptions is automatically provided, saving a considerable amount of time in design space exploration achieving optimisation by reducing global execution time. This paper presents the design process for an FPGA-based multi-MicroBlaze system using SynDEx, and several kernels are developed for the automatic code generation.
  • Keywords
    circuit CAD; circuit optimisation; embedded systems; field programmable gate arrays; high level synthesis; parallel architectures; program compilers; AAA methodology; FPGA- based multi-MicroBlaze system; SynDEx CAD tool; automatic code generation; automatic design process; design space exploration; deterministic image processing application; distributed implementation; global execution time reduction; high level application; multicomponent integration; optimisation; parallel multicomponent architecture; programmable multicomponent architecture; real-time embedded system; Computer architecture; Field programmable gate arrays; Hardware; IP networks; Kernel; Program processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Conference, 2007 15th European
  • Conference_Location
    Poznan
  • Print_ISBN
    978-839-2134-04-6
  • Type

    conf

  • Filename
    7099085