DocumentCode :
706813
Title :
Steady-state error-free RST-controller design: A double diophantine equation approach
Author :
Ostertag, Eric
Author_Institution :
Ecole Nat. Super. de Phys. de Strasbourg, Univ. de Strasbourg I, Illkirch, France
fYear :
1999
fDate :
Aug. 31 1999-Sept. 3 1999
Firstpage :
2841
Lastpage :
2846
Abstract :
RST-controller design by pole placement has been introduced by several authors about fifteen years ago. However, in most of these works, the elimination of steady-state errors resulting from low-frequency inputs has been dealt with only for disturbance inputs, not for reference inputs. As to the latter input, a DC unity gain has been usually taken into account, thus insuring a zero input-output error for stepwise reference inputs, but not for signals of order higher than zero. In this paper, a new design method of RST-controllers is derived, which takes this error criterion into account by means of a secondary diophantine equation, in addition to the usual one.
Keywords :
control system synthesis; linear systems; sampled data systems; DC unity gain; double diophantine equation approach; low-frequency input; pole placement; steady-state error elimination; steady-state error-free RST-controller design; zero input-output error; Delays; Design methodology; Mathematical model; Polynomials; Process control; Steady-state; Transfer functions; RST-controller; non-zero order reference inputs; pole placement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Control Conference (ECC), 1999 European
Conference_Location :
Karlsruhe
Print_ISBN :
978-3-9524173-5-5
Type :
conf
Filename :
7099758
Link To Document :
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