High speed 16-bit digital Vedic multiplier using FPGA

In the present paper our objective is to emphasize the importance of Vedic Mathematics for digital applications. Ancient vedic mathematics not only facilitate the complex mathematical operations but also useful for logical applications. In the present work we are using the concept of Urdhva-tiryakbyham, i.e., vertically and crosswise multiplication and it´s implementation for 16-bit multiplication. This technique optimizes the output in term of steps of calculation and therefore reduces the delay of a digital circuit. We implemented these results with the help of front end language-Verilog. Results obtained from simulation and syntheses have been verified on Spartan 3E FPGA using Xilinx ISE Suite are discussed in details. Obtained results have been compared with the most frequently used multipliers in digital circuits which illustrate 38 % reduction in device utilization and 62% reduction in delay.