DocumentCode
707897
Title
Digitally assisted low-power pipelined analog-to-digital converters
Author
Piatak, Ivan ; Morozov, Dmitry ; Pilipko, Mikhail
Author_Institution
Dept. of the Integrated Electron., St. Petersburg Polytech. Univ., St. Petersburg, Russia
fYear
2015
fDate
2-4 Feb. 2015
Firstpage
254
Lastpage
256
Abstract
In this paper the main aspects in construction of the low-power CMOS pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for a 1.5 bit redundant stage of the pipeline ADC are defined. Examples of the digital and the analog error correction mechanisms for the pipelined ADC in conjunction with the power reduction mechanisms are considered.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; pipeline arithmetic; digitally assisted; error correction mechanisms; low-power CMOS pipelined ADC; low-power pipelined analog-to-digital converters; power reduction mechanisms; CMOS integrated circuits; CMOS technology; DH-HEMTs; Semiconductor device modeling; 1.5 bit redundant stage; SC-circuits; digital error correction; multiplying DAC; operational amplifier; pipelined ADC;
fLanguage
English
Publisher
ieee
Conference_Titel
Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW), 2015 IEEE NW Russia
Conference_Location
St. Petersburg
Print_ISBN
978-1-4799-7305-7
Type
conf
DOI
10.1109/EIConRusNW.2015.7102273
Filename
7102273
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