Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs

Present design methodologies are integrating 10 to 100 embedded functional and storage blocks in a single system on chip and the number is going to increase in the near future. The bus based interconnections are not a suitable choice for MPSoC because of power and latency issue. To address the bus bottleneck for multi core chips, Networks on Chip (NoCs) emerges as an effective and promising alternative. Fault tolerance and quality of service are the potential challenges for NoCs designed for deep submicron era. It was observed that as the system grows, so does the complexity of integrating various components on a chip. In this paper we have proposed a random routing algorithm that has solved deadlock problem along with livelock and packet drop that remains unattended in most NoCs discussion available in literature. This algorithm does handle both single busy node and multiple busy nodes within 2D mesh using reconfigurable paths.