Vericonn: a tool to generate efficient interconnection networks for post-silicon debug

Verification is the most challenging stage in an integrated circuit development cycle. The current techniques used in pre-silicon verification helps the designer catch and fix some errors, but it can not guarantee error free designs for complex integrated circuits in the first fabrication. Some errors are only uncovered after millions of clock cycles. Using post-silicon debug techniques, the designer can monitor the device capturing errors that occur only in a real environment. However, in order to identify an error cause, the related signals should be stored in a trace buffer and then analyzed. Thus, the trace buffer size limits the number of analyzed signals, forcing the designer to use an interconnection fabric to select a signal set to monitor from all tapped signals. In this paper we present a tool to build this interconnection fabric. Our tool is capable to create asymmetric networks like Mux Trees, Clos Networks and Crossbars in Verilog HDL.