Statistical energy study for 28nm FDSOI devices

Author

Kheirallah, Rida ; Galliere, Jean-Marc ; Todri-Sanial, Aida ; Azemard, Nadine ; Ducharme, Gilles

Author_Institution

Univ. Montpellier, Montpellier, France

fYear

2015

fDate

19-22 April 2015

Firstpage

1

Lastpage

4

Abstract

Due to the effects of the Moore´s law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On-Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.

Keywords

CMOS digital integrated circuits; energy conservation; losses; scaling circuits; silicon-on-insulator; statistical analysis; transistors; FDSOI devices; Moore´s law; bulk CMOS; current technology; deep submicron devices; delay; fully depleted silicon-on-insulator technology; parametric yield loss; process variability; process variations; size 28 nm; static power trade-off; statistical energy study; subthreshold circuits; superior energy efficiency; transistor behavior; CMOS integrated circuits; Computational modeling; Delays; Fluctuations; Logic gates; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2015 16th International Conference on

Conference_Location

Budapest

Print_ISBN

978-1-4799-9949-1

Type

conf

DOI

10.1109/EuroSimE.2015.7103149

Filename

7103149