A multilevel VR implementation and MIMO control scheme for vertically-stacked microprocessor cores

Falling supply voltages and increasing parallelism in digital systems pose significant challenges to voltage regulators. Efficient power conversion is especially hampered by very low conversion ratios when supplying low voltage processors from a intermediate DC bus. A recently proposed solution to this problem is to leverage partial power processing architectures which allow to connect multiple loads in series while still regulating the voltage across each load independently of the individual load currents. This work advances the approach by developing a general dynamical system model and control scheme for this architecture. A hardware prototype of a power converter supplying four low-voltage loads from a 12 V supply was developed to demonstrate the proposed control scheme and the efficiency advantages of this architecture. Experimental results show that independent regulation and up to 98% system efficiency can be achieved with load voltages ranging from 0.8-1.4V.