Usage based predictive transistor aging model to optimize test limits on IO circuits

For reliability, it is crucial to understand the impact of aging on a component to insure that performance specifications are met throughout the design lifetime. This paper describes a Monte Carlo based predictive modeling framework to comprehend aging on a GPIO interface in 32nm Intel chipset product. This model incorporates component use conditions such as operating temperatures in the field and platform performance attributes. Use conditions are applied to enable this model to closely match expected population behavior in the field. These results were then used to optimize operating spec parameter values so as to reduce design overhead and product development costs.