DocumentCode :
708609
Title :
Employing optimal experimental design to optimize the accelerated life test plan for TDDB
Author :
Lingxiao Cheng ; Xiaofeng Xu ; Yang, SiYuan Frank ; Chien, Wei-ting Kary
Author_Institution :
Semicond. Manuf. Int. Corp., Shanghai, China
fYear :
2015
fDate :
26-29 Jan. 2015
Firstpage :
1
Lastpage :
6
Abstract :
Time Dependent Dielectric Breakdown (TDDB) is one of the major indices to evaluate the Gate Oxide Integrity (GOI) reliability of Integrated Circuit (IC) devices. Permutation and combination theory helps to derive the many combinations of temperature and voltage stress levels to determine TDDB parameters (i.e., γ and Ea) with a pre-specified sample size. In this work, a statistical tool (JMP10) with optimal experimental design platform for accelerated life test (ALT) is employed to select stressing conditions, to optimize the ALT test plan with a special distribution of sample size for each stressing condition, to model parameter estimation, and to predict lifetimes. Comparing our proposed DOE method to the most popular conventional method, we find our DOE method is better from both theoretical and experimental standpoints. Based on this study, we propose an optimized combination of stressing conditions and sample size allocation for each stress condition. Our proposed method saves capacity, shortens half of the test time, and obtains a narrower confidence interval (CI) of the estimated TDDB lifetime.
Keywords :
design of experiments; electric breakdown; integrated circuit reliability; life testing; parameter estimation; statistical testing; ALT plan; CI; DOE method; GOI; IC devices; JMP10; TDDB parameter estimation; accelerated life test plan optimization; combination theory; confidence interval; design of experiment method; employing optimal experimental design; gate oxide integrity; integrated circuit device reliability; prespecified sample size; sample size allocation; statistical tool; stressing condition selection; temperature stress levels; time dependent dielectric breakdown; voltage stress levels; Acceleration; Life estimation; Logic gates; Manufacturing; Reliability engineering; Stress; γ; Confidence Interval; Design of Experiment; Ea; Gate Oxide; Time Dependent Dielectric Breakdown;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability and Maintainability Symposium (RAMS), 2015 Annual
Conference_Location :
Palm Harbor, FL
Print_ISBN :
978-1-4799-6702-5
Type :
conf
DOI :
10.1109/RAMS.2015.7105185
Filename :
7105185
Link To Document :
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