DocumentCode
708683
Title
Integrated 60-V class-D power output stage with 95% efficiency in a 0.13μm SOI BCD process
Author
El Khadiri, Karim ; Qjidaa, Hassan
Author_Institution
Lab. d´Electron., Signaux, Syst. et d´Inf. (LESSI), Sidi Mouhamed Ben Abbellah Univ., Fez, Morocco
fYear
2015
fDate
25-26 March 2015
Firstpage
1
Lastpage
6
Abstract
In this paper we present a highly-efficient 60V class-D power stage design in a 0.13μm SOI-based BCD process. The integrated output stage consists of a full H-bridge, level shifter, ramp generator, comparator, integrator, and preamplifier. Its performance was found to be better than previously published output stages implemented in SOI based BCD processes, which are typically more complex and costly. The achieved results demonstrate that second-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high end audio applications (THD & 0.029%). The output stage has a maximum efficiency of 95% and delivers up to 600mW into a 8Ω Bridge-Tied Load (BTL) with a total area of 1.5 mm2.
Keywords
BIMOS integrated circuits; bridge circuits; comparators (circuits); harmonic distortion; integrating circuits; preamplifiers; ramp generators; silicon-on-insulator; BTL; Class-D power output stage; H-bridge; SOI BCD Process; THD; bridge-tied load; comparator; integrator; level shifter; preamplifier; ramp generator; second-order class-D amplifier; size 0.13 mum; total harmonic distortion; voltage 60 V; Electromagnetic interference; Generators; Logic gates; Power transistors; Pulse width modulation; Switches; Transistors; BCD; Class-D audio amplifier; Pulse-width-modulation; SOI; Triangle-wave generator;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Systems and Computer Vision (ISCV), 2015
Conference_Location
Fez
Print_ISBN
978-1-4799-7510-5
Type
conf
DOI
10.1109/ISACV.2015.7106184
Filename
7106184
Link To Document