Reducing power-supply and ground noise induced timing jitter in short pulse generation circuits

This paper presents a study of power-supply noise and ground noise impact on the timing properties of short pulse generation circuits. The timing jitter of the measured pulses is mainly from the trigger pulse generator in the circuit consisting of conventional CMOS inverters and NAND gates. Furthermore, the response surface model combined with Latin Hypercube Sampling (LHS) is proposed to model the timing jitter of short pulse generation circuits. The analytical model is verified with Cadence using 0.13 μm CMOS technology. In order to reduce the timing jitter, MOS current-mode logic (MCML) circuits are used in the trigger pulse generator. Up to 50% improvement on the timing jitter can be obtained, due to the differential structure of MCML circuits.