C-based RTL design method for circuit switched network on chips

Author

Fujiya, Kensuke ; Isshiki, Tsuyoshi ; Dongju Li ; Kunieda, Hiroaki

Author_Institution

Dept. of Commun. & Comput. Eng., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2015

fDate

22-24 March 2015

Firstpage

1

Lastpage

6

Abstract

Network-on-Chips (NoCs) are needed to interconnect the cores which are processors and memories in Systems on Chips (SoCs). For designing new NoCs, highly accurate simulation and efficient design procedure are desired. In this paper, we present C-based RTL design method for circuit switched NoC in which RTL structure of NoC is directly described in dataflow C coding style and a fast simulation and verification model by the same C code. Also, we show how the method is used to accelerate the design and verification of the NoC by designing a simple NoC architecture. The entire C model consists of about 200 lines, including C header file. Also, it generates the RTL descriptions which consists of 1,500 lines of Verilog code.

Keywords

C listings; circuit switching; hardware description languages; logic CAD; network-on-chip; C-based RTL design method; RTL description; Verilog code; circuit switched NoC; circuit switched network-on-chips; register transfer level; systems-on-chips; Computer architecture; Design methodology; Integrated circuit modeling; Logic gates; Registers; Switching circuits; System-on-chip; C-based design; Network on Chip; design automation; high level synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Communication Technology for Embedded Systems (IC-ICTES), 2015 6th International Conference of

Conference_Location

Hua-Hin

Type

conf

DOI

10.1109/ICTEmSys.2015.7110822

Filename

7110822