A testable design for electrical interconnect tests of 3D ICs

Author

Odoriba, Akihiro ; Umezu, Shoichi ; Hashizume, Masaki ; Yotsuyanagi, Hiroyuki ; Binti Ashikin Ali, Fara ; Shyue-Kung Lu

Author_Institution

Tokushima Univ., Tokushima, Japan

fYear

2015

fDate

14-17 April 2015

Firstpage

718

Lastpage

722

Abstract

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation. It is shown by the experiments that a hard open defect and a resistive open defect can be detected at a test speed of 1GHz.

Keywords

integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D ICs; IEEE 1149.1 test circuit; Spice simulation; electrical interconnect tests; frequency 1 GHz; open defect detection; test input vector; testable design method; Discrete Fourier transforms; Electrostatic discharges; Integrated circuit interconnections; Integrated circuit modeling; Testing; Three-dimensional displays; 3D IC; Design for Testability; Electrical Test; Open Defect; Through-Silicon Via;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging and iMAPS All Asia Conference (ICEP-IACC), 2015 International Conference on

Conference_Location

Kyoto

Print_ISBN

978-4-9040-9012-1

Type

conf

DOI

10.1109/ICEP-IAAC.2015.7111105

Filename

7111105