Title :
Evaluation of residual stress caused by flip-chip bonding process using piezo-resistor embedded test element group chips
Author :
Enami, Toshio ; Nanami, Kyosuke ; Horiuchi, Osamu ; Young-Gun Han ; Tomokage, Hajime
Author_Institution :
Dept. of Electron. Eng. & Comput. Sci., Fukuoka Univ., Fukuoka, Japan
Abstract :
The stress of ICs caused by flip-chip bonding process is evaluated using piezo-resistor embedded test element group (TEG) chips. The TEG size is 9 × 9 mm2 with 550 μm in thickness. After non-conductive film (NCF) coating, the TEG chip is connected to the substrate by flip-chip bonding. The stress inside the chip was obtained in each process of flip-chip bonding by measuring the change in piezo-resistance. After bonding, the compressive stress is high in the center of TEG chips and the stress was lower towards the corner. The stress at elevated temperatures up to 123 °C is also measured. The compressive stress decreases with increasing temperature. The comparison between NCF and under-fill (UF) materials is performed through the same process.
Keywords :
bonding processes; coating techniques; flip-chip devices; internal stresses; piezoresistive devices; resistors; IC stress; NCF coating; TEG chips; UF materials; compressive stress; flip-chip bonding process; nonconductive film coating; piezo-resistor embedded test element group chips; residual stress evaluation; under-fill materials; Bonding; Flip-chip devices; Residual stresses; Semiconductor device measurement; Substrates; Temperature measurement; flip-chip bonding; non-conductive film; residual stress;
Conference_Titel :
Electronics Packaging and iMAPS All Asia Conference (ICEP-IACC), 2015 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-4-9040-9012-1
DOI :
10.1109/ICEP-IAAC.2015.7111119
