Power debug on Fully Integrated Voltage Regulators (FIVR) circuitry introduced deep low power states

FIVR circuitry reaching ~90% power peak efficiency has been implemented on microprocessors made from the world´s first 3-dimensional tri-gate 22nm technology node. Post silicon debug techniques to address new challenges imposed on design validation, circuit characterization, and power debug on deep low power core, system, and IO states have been established. Faster and better root-cause analysis results demonstrated that newly introduced power debug techniques can also extend to 14nm FIVR circuits.