Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs

Author

Narasimham, Balaji ; Wang, Jung K. ; Vedula, Narayana ; Gupta, Saket ; Bartz, Brandon ; Monzel, Carl ; Chatterjee, Indranil ; Bhuva, Bharat L. ; Schrimpf, Ronald D. ; Reed, Robert A.

Author_Institution

Broadcom Corp., Irvine, CA, USA

fYear

2015

fDate

19-23 April 2015

Abstract

Dual- and triple-well bulk CMOS SRAMs fabricated at the 28-nm node were tested using alpha particles and heavy-ions over a range of supply voltages. Dual-well SRAMs have better Multiple Cell Upset (MCU) cross sections and spread for nominal voltage, while triple-well SRAMs are better for reduced voltages. TCAD simulations show that single-event upset reversal due to charge confinement is responsible for improved soft error rate (SER) performance at low voltage operation for triple-well SRAMs.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit testing; radiation hardening (electronics); sensitivity analysis; MCU cross sections; SER performance; TCAD simulations; alpha particles; charge confinement; dual-well CMOS SRAMs; heavy-ions; improved soft error rate performance; multicell upset soft error sensitivity; single-event upset; size 28 nm; supply voltage; triple-well CMOS SRAMs; Alpha particles; CMOS integrated circuits; Error analysis; Layout; Low voltage; Random access memory; Transistors; MCU; SRAM; alpha particle; dual-well; heavy ion; linear energy transfer (LET); soft error rate(SER); triple-well;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112679

Filename

7112679