Circuit delay variability due to wire resistance evolution under AC electromigration

Electromigration (EM) in signal interconnects can induce voids, and the evolution of these voids may cause the wire resistance to increase with time. Previous approaches use the mean time to failure metric based either on a fixed resistance increase or open circuit failure criterion. This work shows that even noncatastrophic EM on critical paths may cause performance degradation, resulting in incorrect circuit operation. HSPICE-based Monte Carlo simulations on a set of on-chip structures are performed to quantify the impact of EM on circuit performance degradation.