Stochastic and topologically aware electromigration analysis for clock skew

An important link between individual component-level EM failures and the failure of the associated system is established in this work. Conventional EM methodologies are based on the weakest link assumption, which deems the entire system to fail as soon as the first component in the system fails. With a highly redundant circuit topology - that of a clock grid - we present algorithms for EM assessment, which allow us to incorporate and quantify the benefit from system redundancies. We demonstrate that unless such an analysis is performed, chip lifetimes are underestimated by over 2x.