Title :
Improved GGSCR layout for overshoot reduction
Author :
Zaichen Chen ; Mertens, Robert ; Reiman, Collin ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
A new layout of the GGSCR ESD protection device is proposed for transient voltage overshoot reduction. The superior performance of the modified layout is verified in 65nm CMOS technology. Even with the modified layout, key layout spacings, such as the well-tap spacing and the anode to cathode spacing, affect the overshoot voltage. An n-well triggered version of the GGSCR is compared with the usual p-well triggered device and is shown to have larger overshoot. Finally, the susceptibility of the trigger GGNMOS to undergo early failure is investigated.
Keywords :
CMOS integrated circuits; electrostatic discharge; protection; thyristors; transients; CMOS technology; ESD protection; Si; anode-cathode spacing; early failure; grounded-gate NMOS triggered SCR; improved GGSCR layout; key layout spacings; n-well triggered version; size 65 nm; transient voltage overshoot reduction; well-tap spacing; Anodes; Cathodes; Current measurement; Junctions; Layout; Thyristors; Voltage measurement; ESD; GGSCR; overshoot;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
DOI :
10.1109/IRPS.2015.7112720
