Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300^oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300^oC for 30min. As the annealing temperature increase higher than 400^oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.