Title :
Scenario for catastrophic failure in interconnect structures under chip package interaction
Author :
Omiya, Masaki ; Kamiya, Shoji ; Shishido, Nobuyuki ; Koiwa, Kozo ; Sato, Hisashi ; Nishida, Masahiro ; Suzuki, Takashi ; Nakamura, Tomoji ; Suzuki, Toshiaki ; Nokuo, Takeshi
Author_Institution :
Dept. of Mech. Eng., Keio Univ., Yokohama, Japan
Abstract :
This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.
Keywords :
copper; dielectric materials; failure analysis; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; mechanical properties; semiconductor devices; CPI; cap layer; catastrophic failure; chip package interaction; copper interconnect; copper line; insulating layer; interconnect structure; interfacial strength; low-k material; mechanical property; reliability issue; semiconductor device; Adhesives; Copper; Delamination; Integrated circuit interconnections; Numerical models; Reliability; Stress; chip-package interaction; copper line; crack; interfacial strength; low-k; numerical simulation;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
DOI :
10.1109/IRPS.2015.7112751