Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages

BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20nm FinFET for two types of 6T SRAM cells, High-Speed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of V_dd reduction on time-zero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified.